1. Field of the Invention
The present invention relates to a scheduling circuit and a scheduling method used for the same. More particularly, the present invention relates to a scheduling technique for establishing a priority between a plurality of service classes in the same port and then carrying out a scheduling.
2. Description of the Related Art
Conventionally, as this type of a scheduling technique, a scheduling technique is well known which employs a plurality of M×N schedulers and then establishes a priority between a plurality of service classes in the same port. This technique is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 9-326828).
FIG. 1 shows a configuration of a scheduling circuit used for the above-mentioned technique. In this scheduling circuit, connection assignment requests S511, S522, . . . , S52k respectively corresponding to k kinds of service classes in which priorities are different from each other are inputted to M×N schedulers 51, 52, . . . , 5k in the order starting with the service class having a higher priority and then carries out the scheduling.
The respective M×N schedulers 51, 52, . . . , 5k carry out scheduling operations i.e. connection assignments independently of each other, and output connection assignment results S521, S522, . . . , S52k, respectively. Because the respective M×N schedulers 51, 52, . . . , 5k carry out the scheduling operations independently of each other, there may be a fear that two or more M×N schedulers give the connection assignments to one input port or output port.
However, when the connection is actually done, the two or more connection assignments must not be given to the one input or output port. Thus, this requires an assignment result arbitration circuit 60 to carry out an arbitration between the output connection assignment results S521, S522, . . . , S52k.
In the conventional scheduling technique, let us suppose that in a case of k=3, connection assignment results for three service classes through the M×N schedulers 51, 52, and 53, are as shown on a middle portion of FIG. 2.
In this case, when the arbitration is performed in the assignment result arbitration circuit 60 by employing in the order starting with the assignment result of the service class having the higher priority, the arbitrated result shown as a matrix on a bottom portion of FIG. 2 is obtained. Within the matrix of the arbitrated result, a circular mark represented by a solid line indicates the actually assigned connection, and a circular mark represented by a dashed line indicates a lost connection because of the arbitration. A numeral within the circular mark indicates the priority.
When the arbitrated result is considered, there is the connection lost by the arbitration in the assignment result arbitration circuit 60, although the connection assignments were performed by the M×N schedulers 51, 52, and 53.
If assignment conditions of service classes having a higher priority are known in advance, there may be a case that another connection assignment is possible. If such an assignment is possible, a transfer efficiency is dropped in the conventional technique. For example, if the assignment conditions of the service classes having the higher priority are known in advance, it is possible to assign a connection in a manner represented by a star mark of FIG. 2. Thus, there is no connection lost by the arbitration. Hence, the transfer efficiency is never dropped.
The above-mentioned problem is caused by such a fact that the port assignment result is not shared by the schedulers when the scheduling operations are performed by the plurality of M×N schedulers.
As a related technique, Japanese Laid Open Patent Application (JP-A-Heisei, 10-117200) discloses a switch, a cross connection switching device, a connection device, and a routing method in a switch. This technique is provided with a connection unit which is connected between an input port of a cross connection switching unit and a plurality of data units and can be driven so as to transfer data to the input port from the different data units at times different from each other. Thus, a large number of data ports can be accommodated without restriction on the number of input output ports of cross connection switching units.
Japanese Laid Open Patent Application (JP-A-Heisei, 11-88374) discloses a large capacity of multiple-class core ATM switch architecture. In this architecture, a switch effectively adjusts real time and non-real time multiple-cast flows. The switch is provided with a fast core module for mutually connecting input/output modules each having a large capacity of a buffer and an intelligent scheduling/buffer management mechanism. Scheduling can be achieved by using a new dynamic rate control for controlling an inner congestion and then attaining a fare throughput performance between flows competing in a switch bottleneck section. In a method for controlling a dynamic rate, the flow is controlled at a rate based on a congestion information monitored by the bottleneck section in the switch. A rate in which a dynamic rate component for fairly distributing a non-usage bandwidth is added to a minimum service rate is insured for each switch flow.